1. Field of the Invention
The present invention relates to an information processing-apparatus that has an instruction set comprising variable length instructions, and that executes a plurality of instructions concurrently, and more particularly to an instruction processing unit for loading a plurality of instructions into an execution stage.
2. Description of the Related Art
It is known to provide an information processing apparatus that executes a plurality of instructions concurrently (refer to Japanese Unexamined Patent Publication Nos. 6-89173 and 3-255530). In this information processing unit for concurrent execution of a plurality of instructions, as an execution stage is freed, the next sequence of instructions is loaded simultaneously into the execution stage to start the execution of the instructions.
As for the instruction word length, variable instruction length may be employed, depending on the logic specification used. When dealing with such instructions differing in word length, selecting instructions to be loaded into the execution stage requires first interpreting the first instruction, only after which the starting location of the next instruction can be determined. This makes it difficult to execute a plurality of instructions concurrently.
Furthermore, with increasing speed of the system cycle in recent years, there has been an increasing need to enable instructions to be selected at high speed while reducing the amount of circuitry involved.
An object of the present invention is to provide an instruction control apparatus that enables a plurality of instructions of different instruction lengths to be selected simultaneously from an instruction buffer.
Another object of the invention is to reduce the amount of circuitry and achieve high speed processing in an instruction control apparatus that enables a plurality of instructions of different instruction lengths to be selected simultaneously from an instruction buffer.
The present invention has been devised to achieve the above objects. The instruction control apparatus of the invention comprises: address unit holding an address from which to fetch an instruction word, and for updating the address; storage unit holding the fetched instruction word; a fetch control circuit which, prior to instruction execution in an execution stage, fetches one or more instruction words into the storage unit in accordance with the address indicated by the address unit; and a selection circuit which selects a plurality of instructions to be loaded into the execution stage. The selection circuit first selects a portion of an instruction sequence fetched in the storage unit, starting from the beginning of the next instruction word to be loaded into the execution stage, pointed to by a pointer, and extending until reaching a maximum length of instructions that can be loaded into the execution stage, and then, from within the selected portion, selects the plurality of instructions to be loaded into the execution stage, based on a minimum instruction length unit and on the length of each of the instructions.
According to the present invention, since the selection circuit performs the selection in two stages, a plurality of instructions can be selected simultaneously and be executed concurrently in the execution stage.
The instruction control unit of the present invention may be provided with a plurality of loading ports ports for holding the instructions selected by the selection circuit. Each of the plurality of loading ports has a length shorter than the maximum instruction length of instructions to be held therein, and when the length of the instruction to be loaded is longer than the length of the loading port length, the instruction is divided and held between the plurality of loading ports. By using a plurality of such small loading ports, each port is reduced in size, and the selection circuit is also reduced in size. Furthermore, by limiting the execution stage that performs a long instruction word, the circuitry of the execution stage can be reduced.
Further, in the present invention, the instruction word is fetched, not from the starting address of the instruction sequence, but from a designated byte boundary, and a portion of the starting address of the instruction sequence is set so that the initial value of the pointer shows an offset from the designated byte boundary to the instruction sequence, and so that the pointer can point to the beginning of the instruction sequence. According to this embodiment, the need for instruction fetch data alignment can be eliminated.